Method of diagnosing circuit layout and computer system for performing the same

ABSTRACT

A method of diagnosing a circuit layout and a computer system for performing the method. First, a second file is established to record a layout arranging rule, and a first file recording the real circumstance of a circuit layout is read out with the computer system. A diagnosing program is then executed to compare the first file and the second file and to check whether the circuit layout violates to the layout arranging rule. In addition, the diagnosing program is executed to search the first file and to find out which group of power inputting test pads has a total amount of the power inputting test pads less than a safety value, wherein an additional power inputting test pad is required for this group. The diagnosing program is further executed to find out which test pads have an interval less than a safety distance, wherein the interval of the test pads should be amended. By any means, the computer system can rapidly and exactly find out the problem(s) of the arrangement for the test pads in the circuit layout so as to save manpower and time.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to circuit layout designs and, in particular, toa method of diagnosing a circuit layout and a computer system forperforming the method, which are used to diagnose whether thearrangement of the test pads of the circuit layout is sufficient so asto prevent the essential test pad being neglected and not established.

2. Related Art

To cooperate with an in-circuit test (ICT), the contemporary circuitlayout design must include the design for test except the design forfunction. This makes the final circuit board product have not onlyfunctional circuits, but also sufficient test pads for contacting withprobes of the in-circuit tester so as to test whether the function andquality of the circuit board are correct.

In more specific, there are some essential test pads, which are notestablished, in the final circuit layout, so that some items tested withthe in-circuit tester may have test errors since the final circuit boardproduct lacks of the test pads. To solve this problem, it usually needsto manually test that whether the finished circuit layout is shorted ofthe test pad or test pads before the fabrication of the film. Thus, thefinished circuit board product manufactured according to the circuitlayout can have enough test pads for the requirement of in-circuit test.

However, since the circuit layout is manually tested, the testingprocedure is time and personnel consuming. Moreover, the accuracy of themanually testing is poor. It makes the above-mentioned problem ofneglecting test pads is not solved completely and effectively.

SUMMARY OF THE INVENTION

It is therefore, the invention is to provide a method of diagnosing acircuit layout and a computer system to perform the method, wherein thecomputer system can rapidly diagnose whether the arrangement of the testpads on the circuit layout matches the anticipation, so that the circuitboard product fabricated according to the diagnosed circuit layout canhave enough test pads to fit the requirement of the in-circuit test.

The circuit layout includes a plurality of pin pads, a plurality of testpads, and a plurality of nets connecting the pin pads and the test pads.All data of the pin pads, the test pads, and the nets are defined in atleast one first file.

In order to test whether the arrangement of the test pads on the circuitlayout matches the anticipation, in the invention, a layout arrangingrule is firstly established to regulate the fundamental requirements ofthe circuit layout. The layout arranging rule is specifically defined ina second file. Therefore, a computer system can be used to read thecontents of the first and second files, and then executes a diagnosingprogram to compare the first and second files. Accordingly, the circuitlayout violated to the layout arranging rule can be found via thecomparison between the first and second files. For example, the layoutarranging rule defined in the second file records the names of the pinpads and whether the pin pad or pin pads are absolutely necessarilyconnected to the test pad or test pads. Then, once the first file, whichrecords the name of each of the pin pads and connecting statuses of eachof the pin pads showing whether the pin pads are connected to the testpads, is read, the executed diagnosing program can find out which pinpad in the circuit layout is regulated to be an absolutely necessarytest pad and is actually unconnected to any test pad.

Besides, since the first file records the real circumstance of thecircuit layout, the diagnosing program, under a proper design, canfurther search the first file and find out which test pad is a powerinputting test pad, which power inputting test pad belongs to the samegroup, and which group of the power inputting test pads having the totalamount less than a safety value and needing an additional powerinputting test pad.

Similarly, the diagnosing program, under a proper design, can furtherfind out the shortest interval between two neighboring test pads, andwhich test pads having an interval less than a safety distance andneeded to be amended.

The invention uses a computer system to read the first and second filesand to execute the diagnosing program, so that the improper arrangementof the test pads in the circuit layout is then found rapidly. Finally, areport recording the diagnosing results is generated. The designersdesigning the circuit and layout can improve their designs according tothis report. Thus, circuit board products, which fit the requirements inboth function and testing, are obtained.

Compared with the conventional manually testing of a circuit layout, theinvention provides a computer system to perform the diagnosing (testing)of the circuit layout, which makes the diagnosing procedure faster andmore correct, and saves more personnel and time. Thus, the invention ishighly useful and non-obvious.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription given hereinbelow illustration only, and thus is notlimitative of the present invention, and wherein:

FIG. 1 is a partial enlarged view showing a portion of a circuit layoutaccording to a preferred embodiment of the invention;

FIG. 2 is a schematic illustration showing a portion of the content ofthe first file according to the preferred embodiment of the invention;

FIG. 3 is a schematic illustration showing a portion of the content ofthe third file according to the preferred embodiment of the invention;

FIG. 4 is a schematic illustration showing a portion of the content ofthe second file according to the preferred embodiment of the invention;

FIG. 5 is a block diagram showing an overview according to the preferredembodiment of the invention;

FIG. 6 is a flow chart showing the method of diagnosing a circuit layoutwith a computer system according to the preferred embodiment of theinvention; and

FIG. 7 is a schematic illustration showing the content of the finallyreport according to a preferred embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

To illustrate the invention, the circuit layout 1 shown in FIG. 1 istaken as an example to describe how the method and computer systemaccording to a preferred embodiment of the invention test whether therequirements in testing of the circuit layout 1 is enough. Although theFIG. 1 only shows a portion of the circuit layout 1, those who skilledin the art should know that the illustrated portion of the circuitlayout 1 is sufficient to present the whole circuit layout 1 and tosupport the following description.

The circuit layout 1 includes a plurality of pin pads 10, a plurality ofnets 11 for connecting the pin pads 10, and a plurality of test pads 12for testing. The test pads 12 are respectively connected to thecorresponding pin pads 10 via the nets 11. The test pads 12 furtherinclude a plurality of groups of power inputting test pads 120, whichrelate to the power input. Each group of the power inputting test pads120 corresponds to one of the input voltages of different levels. Forexample, the group of the power inputting test pads 120 a has a groupname of “+5V” and is used to input +5V voltages, and the group of thepower inputting test pads 120 b has a group name of “+3.3V” and is usedto input +3.3V voltages.

Although the circuit layout 1 is a graphic file generated from a layoutsoftware, the information in the graphic file circuit layout 1 (as shownin FIG. 1), such as the names, coordinates, numbers, areas, and thelikes of the pin pads 10, nets 11, test pads 12 and power inputting testpads 120, can be transformed into one or more text files. Thistransformation function is usually provided by the present layoutsoftware. The first file 2 shown in FIG. 2 is an illustration showing atransformed text file by the present layout software. The first file 2shows the column titles including the part name 21, the pin number 22,the index 23, the X coordinate of the pin pad 24, the Y coordinate ofthe pin pad 25, the layer name 26, the net name 27, and the nail(s) 28,wherein the index 23 means the name of the pin pad, and the nail(s) 28means that whether the pin pad 10 is connected to the corresponding testpad 12. In the first file 2, the value of nail(s) 28 is “0” when the pinpad 10 is connected to the test pad 12, and the value of nail(s) 28 isblank when the pin pad 10 is unconnected to the test pad 12.

FIG. 3 shows a third file 5, which is also a transformed text filegenerated by present layout software corresponding to the circuit layout1. The third file 5 lists the column titles, such as the nail(s) 51, theX coordinate of the test pad 52, the Y coordinate of the test pad 53,the test pad type 54, the test pad grid 55, the test pad area 56, thenet number 57, the net name 58, and etc, and information (or data)thereof.

As shown in FIG. 4, the second file 3 records the column titles, such asthe index 31, the suggestion 32, and the priority 33, and theinformation (or data) thereof. As shown in FIG. 5, the information isthe layout arranging rule 99 established according to the testrequirements. The information corresponding to the priority 33represents whether one pin pad 10 (as shown in FIG. 1) is absolutenecessarily to be connected to one test pad 12 (as shown in FIG. 1). Forexample, the pin pad 10 named A2 is defined to be “Absolute necessary”,while the pin pad 10 named A6 is defined to be “Not essential”.

A safety value 47 and a safety distance 49 are established according tothe layout arranging rule 99. The safety value 47 and the safetydistance 49 are defined in a diagnosing program 4.

With reference to FIG. 5, the first file 2, the third file 5, the secondfile 3, and the diagnosing program 4 are all inputted to a computersystem 6. In the current embodiment, the computer system 6 performs thediagnosing program 4 to diagnose whether the circuit layout 1 matchesthe layout arranging rule 99 as the followings:

1. The pin pad 10, which is defined as “absolute necessarily” to beconnected to the test pad 12, must connect to one test pad 12 in thecircuit layout 1.

2. The total amount 67 of the power inputting test pads 120 in eachgroup of the circuit layout 1 must be greater than 5.

3. The interval 69 between two neighboring test pads 12 must be longerthan 50 mils.

According to the preferred embodiment of the invention, the computersystem 6 including at least a central process unit (CPU) and a storageunit is used to read the first file 2, the third file 5, and the secondfile 3, and to execute the diagnosing program 4. Thus, the portions ofthe information recorded in the first file 2 and violated the layoutarranging rule 99 are picked out, and the test pads recorded in thethird files 5, having the same group name, and violated the safety value47 and the safety distance 49 defined in the diagnosing program 4 arefound out. The first file 2 and the third file 5 can represent the realcircumstance of the circuit layout 1, and the safety value 47 and thesafety distance 49 defined in the diagnosing program 4 can represent thelayout arranging rule 99 of the circuit layout 1. Therefore, after thetesting procedures described above, any portion of the circuit layout 1,which is violated the layout arranging rule 99, would be find out by thecomputer system 6, and then be listed in a report 7.

More specifically speaking, the computer system 6 can perform thefollowing steps to diagnose whether the circuit layout 1 matches theanticipated requirement, the layout arranging rule 99. Referring to FIG.6, the steps includes:

Reading the first file 2, which is previously obtained;

Reading the second file 3, which is previously established;

Executing the diagnosing program 4 to compare the contents of the firstfile 2 and the second file 3 so as to find the difference informationbetween the first file 2 and the second file 3, and, for example, tofind the portion of the circuit layout 1 violated the layout arrangingrule 99;

Listing the pin pad 10, which violates the layout arranging rule 99 andrequires the connection with an additional test pad 12;

Reading the third file 5, which is previously obtained;

Executing the diagnosing program 4 to count the total amount of thepower inputting test pad 67 in each group, and, for example, to find outevery power inputting test pad 120 inside the third file 5 and toaccumulate the total amount of the power inputting test pads 67 with thesame group name;

Obtaining a difference 65 between the previously obtained safety value47 and the total amount of the power inputting test pads 67 in eachgroup, wherein the safety value 47, in this embodiment, is 5; and

Determining whether the difference value 65 is greater than zero,wherein when the difference value 65 is greater than zero, the data ofthe difference value 65 is set to be “0”, and when the difference value65 is not greater than zero, the difference value 65 and the group nameof this group of the power inputting test pads 120 are listed.

In addition, the diagnosing program 4 may be further executed tocalculate the interval 69 between two neighboring test pads 12; and tolist the test pads 12 having the interval 69 less than the safetydistance 49, which is 50 mils in the present embodiment.

The diagnosing program 4 is than executed to generate a report 7, whichrepresents the pin pad 10 in the circuit layout 1 violated the layoutarranging rule 99 and requires the connection with an additional testpad 12, the group name of each group of the power inputting test pads120, the corresponding difference value 65, and the test pads 12 havingthe interval 69 less than the safety distance 49.

Since the first file 2 and the second file 3 are both in Excel format,the diagnosing program 4 can be written by the VBA program language. Forexample, according to the value corresponding to the column titled withnail(s) 28 (shown in FIG. 2), the pin pad 10, which is unconnected toany test pad 12, is searched out from the first file 2. After that, thesearched pin pads 10 and the values corresponding to the column titledwith priority 33 of the second file 3 are compared one by one. Thus, thepin pad 10, which is the pin pad 12 of being “absolutely necessarily”connected to the test pad 12 and is actually unconnected to any test pad12, is found.

The diagnosing program 4 can also find the power inputting test pads 120of the same group name, such as “+5V”, and count the total amount 67 ofthe power inputting test pads of each group. The total amount 67 is thencompared with the safety value 47 so as to determine which group has thetotal amount 67 that is insufficient and requires the additional powerinputting test pad 120. As shown in FIG. 3, the total amount 67 of thepower inputting test pad 120 having the same group name of “+5V” is 1,which is less than the anticipated safety value 47, “5”. Thus, 4additional power inputting test pads 120 are required for this group ofthe power inputting test pads 120.

The diagnosing program 4 can further calculate the difference value 65between the interval 69 and the safety distance 49 according to therecorded information of the test pad 12 such as the columns titled withthe X coordinate of the test pad 52, the Y coordinate of the test pad53, the test pad type 54, the test pad grid 55, the test pad area 56,and the group name 58 in the third file 5. The diagnosing program 4 canthen determine which test pads 12 having interval 69 violated therequirements, such as lower than 50 mils.

Finally, the diagnosing program 4 can generate a report 7, which is inExcel format, so as to receive and to record the diagnosing resultsdescribed above. With reference to FIG. 7, the substantial content ofthe report 7 is shown and includes three portions, wherein:

The first portion is used to represent which pin pad 10 is absolutenecessarily to be connected to the addition test pad 12, and, forexample, the pin pad 10 with the group name of “PCI-CK-33M-LPC” is theone that should be connected to the addition test pad 12;

The second portion is used to represent which group of the powerinputting test pads 120 has the total amount 67 less than the safetyvalue 47, such as “5”, and needs the additional power inputting test pad120, and, as shown in FIG. 7, the total amount 67 of the power inputtingtest pads 120 with the group name of “+5V” is 1 and less than the safetyvalue 47, such as “5”, so that 4 additional power inputting test pads120 are required; and

The third portion is used to represent which test pads 12 have theinterval 69 less than the safety distance 49, such as “50 mils”, andneed an increased interval 69, and, as shown in FIG. 7, there are fourtest pads 12 violated the requirement.

It should be noted that the information (or data) presented in the thirdfile 5 could be involved in the first file 2. In other words, thedefinitions of the circuit layout 1 can be completely recorded in thefirst file 2. Accordingly, the diagnosing program 4 can be performedaccording to the first file 2 with added column(s), so as to obtain theinformation stated in the first, second, and third portions of thereport 7.

In the present embodiment of the invention, the computer system 6 isused to read the previously-obtained first file 2 and thepreviously-established second file 3, and then executes the diagnosingprogram 4, which functions comparing, sieving, searching, file buildingand the likes. Thus, the portion of the circuit layout 1, which does notmatch the anticipate requirement, is found through the comparisonbetween the content of the first file 2 and the second file 3. By themeans of the computerized testing, the circuit layout 1 can be rapidlyand exactly tested so as to find out whether the circuit layout 1 canmatch the requirement of design for test, and, in particular, the testpin arrangement.

Compared with the conventional manual testing of a circuit layout, theinvention uses a computer system to process the diagnosing of thecircuit layout. Therefore, the diagnosing method of the invention ismuch faster, more correct, manpower and time saving, useful, andnon-obvious.

Moreover, there is no disclosure, which is the same as or similar to theinvention in the field, disclosed in prior, and the invention could bethus patentable and is filed.

Although the invention has been described with reference to specificembodiments, this description is not meant to be construed in a limitingsense. Various modifications of the disclosed embodiments, as well asalternative embodiments, will be apparent to persons skilled in the art.It is, therefore, contemplated that the appended claims will cover allmodifications that fall within the true scope of the invention.

1. A method of diagnosing a circuit layout defined by at least one firstfile, wherein the first file further comprise data of pin pads, data oftest pads, and data of nets connecting the pin pads and the test pads,the method comprising: establishing a layout arranging rule, wherein thelayout arranging rule is defined in a second file; retrieving the firstfile; and comparing the first file and the second file to check whetherthe circuit layout violates the layout arranging rule.
 2. The method ofclaim 1, further comprising: generating a report to present whether thecircuit layout violates the layout arranging rule.
 3. The method ofclaim 1, the first file further comprising each name of the pin pads anda plurality of connecting statuses of each of the pin pads, wherein theconnecting statuses show whether the pin pads are connected to one ofthe test pads, and the second file further assigning some of the pinpads absolute necessarily connected to one of the test pads.
 4. Themethod of claim 3, further comprising: generating a report to presentwhich connecting status of the pin pads in the first file isinconsistent with the second file.
 5. The method of claim 1, the testpads further comprising a plurality of power inputting test pads,wherein the power inputting test pads are divided into several groups,and each group has a group name and an equivalent input voltage, themethod comprising: specifying a plurality of safety values for anindividual group of the power inputting test pads; searching each of thepower inputting test pads inside the first file and accumulating aplurality of actual total amounts of each group of the power inputtingtest pads; and obtaining an individual difference value of each group ofthe power inputting test pads between the individual safety value andthe actual total amount of power inputting test pads, wherein thedifference value is replaced by zero when the difference is less than orequal to zero.
 6. The method of claim 5, further comprising: generatinga report to present the group name of the power inputting test pads andthe difference value of each group of power inputting test pads of thecircuit layout violating the layout arranging rule.
 7. The method ofclaim 5, wherein the first file further comprises a coordinate of theindividual test pads and an area of the individual test pads, the methodfurther comprising: defining a safety distance; calculating an intervalbetween two of the neighboring test pads; and calculating the distancedifference between the safety distance and the interval between two ofthe neighboring test pads.
 8. The method of claim 7, further comprising:generating a report to present the group name of power inputting testpads and the difference value of the individual power inputting testpads, and indicating the test pads having the interval less than thesafety distance.
 9. The method of claim 7, wherein the first file atleast records: the names of the individual pin pads; the connectingstatuses of the individual pin pads, wherein the connecting statusesshow whether the pin pads are connected to one of the test pads; thegroup name of each group of the power inputting test pads; thecoordinate of each of the test pads; and the area of each of the testpads.
 10. A computer system, comprising at least one central processingunit, at least one storage unit, a first file, a second file, and adiagnosing program stored in the storage unit to diagnose a circuitlayout, wherein: the circuit layout comprises a plurality of pin pads, aplurality of test pads, and a plurality of nets connecting the pin padsand the test pads; data of the pin pads, the test pads, and the nets aredefined in the first file; a layout arranging rule is defined in thesecond file; and the diagnosing program is executed to comparing thefirst file and the second file to check whether the circuit layoutviolates the layout arranging rule.
 11. The computer system of claim 10,wherein the diagnosing program is executed to generate a report topresent whether the circuit layout violates the layout arranging rule.12. The computer system of claim 10, the first file further comprisingeach name of the pin pads and a plurality of connecting statuses of eachof the pin pads, wherein the connecting statuses show whether the pinpads are connected to one of the test pads, the second file furtherassigning some of the pin pads absolute necessarily connected to one ofthe test pads.
 13. The computer system of claim 12, wherein the testingprogram is executed to generate a report to present which connectingstatus of the pin pads in the first file is inconsistent with the secondfile.
 14. The computer system of claim 10, the test pads furthercomprising a plurality of power inputting test pads, wherein the powerinputting test pads are divided into several groups, wherein each grouphas a group name and an equivalent input voltage, the testing programbeing executed to: specify a plurality of safety values for anindividual group of the power inputting test pads; search each of thepower inputting test pads inside the first file and accumulating aplurality of actual total amounts of each group of the power inputtingtest pads; and obtain an individual difference value of each group ofthe power inputting test pads between the individual safety value andthe actual total amounts of the power inputting test pads, wherein thedifference value is replaced by zero when the difference value is lessthan or equal to zero.
 15. The computer system of claim 14, wherein thediagnosing program is executed to generate a report to present the groupname of the power inputting test pads and the difference value of eachgroup of the power inputting test pads of the circuit layout violatingthe layout arranging rule.
 16. The computer system of claim 14, whereinthe first file further comprises a coordinate of the individual testpads and an area of the individual test pads, and the diagnosing programis executed to: define a safety distance; and calculate the distancedifference between the safety distance and an interval between two ofthe neighboring test pads.
 17. The computer system of claim 16, whereinthe diagnosing program is executed to generate a report to present thegroup name of power inputting test pads and the difference value of theindividual power inputting test pads, and indicating the test padshaving the interval less than the safety distance.
 18. The computersystem of claim 16, wherein the first file at least records: the namesof the individual pin pads; the connecting statuses of the individualpin pads, wherein the connecting statuses show whether the pin padsconnect to one of the test pads; the group name of each group of thepower inputting test pads; the coordinate of each of the test pads; andthe area of each of the test pads.